1. Field of the Invention
The present invention relates to an interface circuit and a method of controlling a delay time in the interface circuit, which is capable of suppressing fluctuation in the delay time in signal transmission.
2. Description of the Prior Art
In the prior art, as an interface circuit for communicating signals between a system installing an LSI (large scale integrated circuit) such as a microcomputer and an external device, there has been an interface circuit serving as an input/output cell shown in FIG. 1, for example.
The interface circuit shown in FIG. 1 consists of cascade-connected CMOS inverters 51, 52 each of which is made up of series-connected P-channel FET (Field Effect Transistor), e.g., MOS transistor, and N-channel MOS transistor. The interface circuit, if serves as an input interface circuit, transmits an external signal being supplied to an input terminal 53 to an internal output terminal 54. Also the interface circuit, if serves as an output interface circuit, transmits an internal signal being supplied to an input terminal 53 to an external output terminal 54.
As a similar interface circuit, there has been an interface circuit shown FIG. 2 to have matching in signal timing. Basically this interface circuit is provided on the inner side rather than the interface circuit serving as the input/output cell shown in FIG. 1 (In FIG. 2, a reference 65 denotes the input/output cell.) and has a similar configuration to that shown in FIG. 1. FIG. 2 shows the input interface circuit.
In such interface circuit, there are some cases where fluctuation in the drain current of the transistor is caused by variation in manufacturing processes. Such fluctuation in the drain current is also caused by change in the ambient temperature and variation in the power supply voltage. If such fluctuation in the drain current is caused by these causes, variation in operation speed of the transistor as well as variation in signal transmission time in the interface circuit, i.e., variation in signal delay time are brought about. According to the interface circuit shown in FIG. 2, large variation in delay time of the delay cell causes the problem in timing design between such delay cell and the LSI to be connected and imposes a constraint on improvement in performances of the overall system in the situation that a signal being passed through a delay cell is supplied to other LSIs via the output interface.
Therefore, if such interface circuit is employed, timing design of the system must be conducted while taking account of the fact that the signal delay time in the interface circuit shows about 0.5 to 2.0 times fluctuation of an ordinary reference value. However, such fluctuation serves as a constraint upon improvement in performances of the overall system to thus be an obstacle to improvement in the performances.
FIG. 3 is a circuit diagram showing data transmission routes between LSIs in the prior art. In FIG. 3, a clock output buffer 72 is provided on the output of a clock line in a transmitter side chip 71, a data output buffer 73 is provided on the output of a data line, and a flip-flop (F/F) 74 is provided on the input side of the data output buffer 73. Similarly, a clock input buffer 82 is provided on the input of the clock line in a receiver side chip 81, a data input buffer 83 is provided on the input of the data line, and a flip-flop (F/F) 84 is provided on the inside of the data input buffer 83.
With the above configuration, fluctuation in the delay time in the flip-flop and the logic gate due to variation in power supply voltage, manufacturing process, and use temperature cannot be disregarded. In particular, in high speed data transmission, if timing of the flip-flop is designed to afford a sufficient margin for fluctuation in the delay time in the receiver side chip 81, such sufficient margin forms a barrier against improvement in performances of the overall system.
FIG. 4 is a timing chart illustrating phase difference between a clock signal and a data signal in the prior art. A phase difference of DATA best signal relative to the clock signal is most preferable. However, if a phase difference between DATA worst signal and the clock signal occurs because of fluctuation in the delay time, a most harmful influence is exerted upon performances of the overall system.
Accordingly, in such high speed data transmission, there is necessity of designing timing with due regard to fluctuation in the delay time in the flip-flop because of variation in power supply voltage, process, and temperature.
As described earlier, in the interface circuit in the prior art, there has been caused fluctuation in the signal delay time due to variation in the manufacturing process and the use temperature, variation in the power supply voltage, etc. Consequently, such a disadvantage has been arisen that a high speed operation of the system becomes difficult when the system is designed with regard to these variations.